SanDisk SDSDB-32-201-80 - Industrial Grade Flash Memory Card Manual Page 67
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Secure Digital (SD) Card Protocol Description
SanDisk Industrial Grade SD Product Manual, Rev. 1.0 © 2003 SANDISK CORPORATION -4-15
1) CLK
CMD
2) CLK
CMD
100KHz-400KHz Clocks
Polling less than 50ms interval
1st
1st
2nd
2nd
3rd
3rd
<50ms
<50ms
(ACMD41)
(ACMD41)
Figure 4-9. Host Procedures Waiting for Card to be Ready
• It is an obvious requirement that the clock must be running for the Industrial Grade SD Card to output
data or response tokens. After the last SD Card bus transaction, the host is required to provide eight
(8) clock cycles for the card to complete the operation before shutting down the clock. Following is a
list of various Industrial Grade SD Card bus transactions:
− A command with no response—eight clocks after the host command end bit.
− A command with response—eight clocks after the card response end bit.
− A read data transaction—eight clocks after the end bit of the last data block.
− A write data transaction—eight clocks after the CRC status token.
• The host is allowed to shut down the clock of a “busy” card. The Industrial Grade SD Card will
complete the programming operation regardless of the host clock. However, the host must provide a
clock edge for the card to turn off its busy signal. Without a clock edge the card (unless previously
disconnected by a deselect command -CMD7) will force the DAT0 line down, permanently.
4.6. Cyclic Redundancy Codes (CRC)
The Cyclic Redundancy Check (CRC) is intended for protecting Industrial Grade SD Card commands, responses
and data transfer against transmission errors on the SD Card bus. One CRC is generated for every command and
checked for every response on the CMD line. For data blocks, CRC is generated for each DAT line per transferred
block. The CRC is generated and checked as described in the following:
CRC7
The CRC7 check is used for all commands, for all responses except type R3, and for the CSD and CID registers.
The CRC7 is a 7-bit value and is computed as follows:
generator polynomial: G(x) = x
7
+ x
3
+ 1.
M(x) = (first bit) * x
n
+ (second bit) * x
n-1
+...+ (last bit) * x
0
CRC[6...0] = Remainder [(M(x) * x
7
) / G(x)]
The first bit is the most significant bit of the corresponding bit string (of the command, response, CID or CSD). The
degree n of the polynomial is the number of CRC protected bits decreased by one. The number of bits to be
protected is 40 for commands and responses (n = 39), and 120 for the CSD and CID (n = 119).
- Product Manual 1
- Table of Contents 3
- Table of Contents 5
- 1.1. Scope 8
- 1.2. Product Models 8
- 1.3. System Features 8
- 1.4. SD Card Standard 9
- 1.5. Functional Description 9
- 1.5.10.9. Write Protection 18
- Same as in SD Card mode 18
- 2. Product Specifications 21
- 2.4. System Performance 22
- 2.6. Physical Specifications 23
- Product Specifications 24
- Product Specifications 25
- (2) I Reserved 28
- 3.2. SD Bus Topology 29
- 3.3. SPI Bus Topology 31
- 3.4. Electrical Interface 32
- 3.4.5. Bus Timing 36
- Table 3-7. Bus Timing 36
- • Card busy=LOW (bit 31) 38
- READ_BL_LEN 42
- C_SIZE_MULT+2 43
- WRITE_BL_LEN 44
- Prot 2, Spec V1.01 46
- Table 3-28. Card Status 48
- 4.1. SD Bus Protocol 53
- SPI Operation 58
- CS Asserted ("0") 58
- Note that ACMD41 is an 59
- 4.4. Data Transfer Mode 60
- 4.5. Clock Control 66
- 100KHz-400KHz Clocks 67
- 4.7. Error Conditions 69
- 4.8. Commands 70
- Reserved 71
- 4.10. Responses 77
- 4.11. Timings 79
- 4.11.4. Timing Values 84
- Table 4-17. Timing Values 84
- 5. SPI Protocol Definition 85
- 5.3. Card Registers 99
- 5.4. SPI Bus Timing Diagrams 99
- SPI Protocol Definition 100
- SPI Protocol Definition 101
- Appendix A. Application Note 105
- Interface 106
- Read/Write Mode Selection 108
- Power and Clock Control 108
- Initialization Algorithm 109
- File System Support 109
- Application Note 110
- Ordering Information 112
- Limited Warranty 116
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